Fundamentals of Quantitative Design and Analysis - Computer Architecture: A Quantitative Approach - page 11

FIGURE 1.4 MIPS registers and usage conventions . In addition to the 32 general-purpose
registers (R0-R31), MIPS has 32 floating-point registers (F0-F31) that can hold either a 32-bit
single-precision number or a 64-bit double-precision number.
2. Memory addressing —Virtually all desktop and server computers, including the 80x86, ARM,
and MIPS, use byte addressing to access memory operands. Some architectures, like ARM
and MIPS, require that objects must be aligned . An access to an object of size s bytes at byte
address A is aligned if A mod s = 0. (See Figure A.5 on page A-8.) The 80x86 does not re-
quire alignment, but accesses are generally faster if operands are aligned.
3. Addressing modes —In addition to specifying registers and constant operands, addressing
modes specify the address of a memory object. MIPS addressing modes are Register, Im-
mediate (for constants), and Displacement, where a constant offset is added to a register
to form the memory address. The 80x86 supports those three plus three variations of dis-
placement: no register (absolute), two registers (based indexed with displacement), and
two registers where one register is multiplied by the size of the operand in bytes (based
with scaled index and displacement). It has more like the last three, minus the displace-
ment field, plus register indirect, indexed, and based with scaled index. ARM has the three
MIPS addressing modes plus PC-relative addressing, the sum of two registers, and the sum
of two registers where one register is multiplied by the size of the operand in bytes. It also
has autoincrement and autodecrement addressing, where the calculated address replaces
the contents of one of the registers used in forming the address.
4. Types and sizes of operands —Like most ISAs, 80x86, ARM, and MIPS support operand sizes
of 8-bit (ASCII character), 16-bit (Unicode character or half word), 32-bit (integer or word),
64-bit (double word or long integer), and IEEE 754 floating point in 32-bit (single preci-
sion) and 64-bit (double precision). The 80x86 also supports 80-bit floating point (extended
double precision).
5. Operations —The general categories of operations are data transfer, arithmetic logical, con-
trol (discussed next), and floating point. MIPS is a simple and easy-to-pipeline instruction
set architecture, and it is representative of the RISC architectures being used in 2011. Figure
1.5 summarizes the MIPS ISA. The 80x86 has a much richer and larger set of operations
(see Appendix K).