Hardware Reference
In-Depth Information
FIGURE 5.5 The cache coherence mechanism receives requests from both the core's
processor and the shared bus and responds to these based on the type of request,
whether it hits or misses in the local cache, and the state of the local cache block spe-
cified in the request . The fourth column describes the type of cache action as normal hit or
miss (the same as a uniprocessor cache would see), replacement (a uniprocessor cache re-
placement miss), or coherence (required to maintain cache coherence); a normal or replace-
ment action may cause a coherence action depending on the state of the block in other
caches. For read, misses, write misses, or invalidates snooped from the bus, an action is re-
quired only if the read or write addresses match a block in the local cache and the block is val-
id.
When an invalidate or a write miss is placed on the bus, any cores whose private caches
have copies of the cache block invalidate it. For a write miss in a write-back cache, if the block
is exclusive in just one private cache, that cache also writes back the block; otherwise, the data
can be read from the shared cache or memory.
Figure 5.6 shows a finite-state transition diagram for a single private cache block using a
write invalidation protocol and a write-back cache. For simplicity, the three states of the pro-
tocol are duplicated to represent transitions based on processor requests (on the left, which
corresponds to the top half of the table in Figure 5.5 ), as opposed to transitions based on bus
requests (on the right, which corresponds to the botom half of the table in Figure 5.5 ). Bold-
face type is used to distinguish the bus actions, as opposed to the conditions on which a state
transition depends. The state in each node represents the state of the selected private cache
block specified by the processor or bus request.
 
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