Hardware Reference
In-Depth Information
An Example Protocol
A snooping coherence protocol is usually implemented by incorporating a finite-state control-
ler in each core. This controller responds to requests from the processor in the core and from
the bus (or other broadcast medium), changing the state of the selected cache block, as well as
using the bus to access data or to invalidate it. Logically, you can think of a separate controller
being associated with each block; that is, snooping operations or cache requests for diferent
blocks can proceed independently. In actual implementations, a single controller allows mul-
tiple operations to distinct blocks to proceed in interleaved fashion (that is, one operation may
be initiated before another is completed, even though only one cache access or one bus access
is allowed at a time). Also, remember that, although we refer to a bus in the following descrip-
tion, any interconnection network that supports a broadcast to all the coherence controllers
and their associated private caches can be used to implement snooping.
The simple protocol we consider has three states: invalid, shared, and modified. The shared
state indicates that the block in the private cache is potentially shared, while the modified state
indicates that the block has been updated in the private cache; note that the modified state
im-
plies
that the block is exclusive.
Figure 5.5
shows the requests generated by a core (in the top
half of the table) as well as those coming from the bus (in the botom half of the table). This
protocol is for a write-back cache but is easily changed to work for a write-through cache by
reinterpreting the modified state as an exclusive state and updating the cache on writes in the
normal fashion for a write-through cache. The most common extension of this basic protocol is
the addition of an exclusive state, which describes a block that is unmodified but held in only
one private cache. We describe this and other extensions on page 362.
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