Thread-Level Parallelism - Computer Architecture: A Quantitative Approach - page 354

■ Snooping —Rather than keeping the state of sharing in a single directory, every cache that
has a copy of the data from a block of physical memory could track the sharing status of
the block. In an SMP, the caches are typically all accessible via some broadcast medium
(e.g., a bus connects the per-core caches to the shared cache or memory), and all cache con-
trollers monitor or snoop on the medium to determine whether or not they have a copy of a
block that is requested on a bus or switch access. Snooping can also be used as the coheren-
ce protocol for a multichip multiprocessor, and some designs support a snooping protocol
on top of a directory protocol within each multicore!
Snooping protocols became popular with multiprocessors using micro-processors (single-
core) and caches atached to a single shared memory by a bus. The bus provided a convenient
broadcast medium to implement the snooping protocols. Multicore architectures changed the
picture significantly, since all multicores share some level of cache on the chip. Thus, some
designs switched to using directory protocols, since the overhead was small. To allow the
reader to become familiar with both types of protocols, we focus on a snooping protocol here
and discuss a directory protocol when we come to DSM architectures.
Snooping Coherence Protocols
There are two ways to maintain the coherence requirement described in the prior subsection.
One method is to ensure that a processor has exclusive access to a data item before it writes
that item. This style of protocol is called a write invalidate protocol because it invalidates other
copies on a write. It is by far the most common protocol. Exclusive access ensures that no other
readable or writable copies of an item exist when the write occurs: All other cached copies of
the item are invalidated.
Figure 5.4 shows an example of an invalidation protocol with write-back caches in action.
To see how this protocol ensures coherence, consider a write followed by a read by another
processor: Since the write requires exclusive access, any copy held by the reading processor
must be invalidated (hence, the protocol name). Thus, when the read occurs, it misses in the
cache and is forced to fetch a new copy of the data. For a write, we require that the writing
processor have exclusive access, preventing any other processor from being able to write sim-
ultaneously. If two processors do atempt to write the same data simultaneously, one of them
wins the race (we'll see how we decide who wins shortly), causing the other processor's copy
to be invalidated. For the other processor to complete its write, it must obtain a new copy of
the data, which must now contain the updated value. Therefore, this protocol enforces write
serialization.