Data-Level Parallelism in Vector, SIMD, and GPU Architectures - Computer Architecture: A Quantitative Approach - page 261

FIGURE 4.1 Potential speedup via parallelism from MIMD, SIMD, and both MIMD and
SIMD over time for x86 computers . This figure assumes that two cores per chip for MIMD
will be added every two years and the number of operations for SIMD will double every four
years.
For x86 computers, we expect to see two additional cores per chip every two years and the
SIMD width to double every four years. Given these assumptions, over the next decade the po-
tential speedup from SIMD parallelism is twice that of MIMD parallelism. Hence, it's as least
as important to understand SIMD parallelism as MIMD parallelism, although the latter has
received much more fanfare recently. For applications with both data-level parallelism and
thread-level parallelism, the potential speedup in 2020 will be an order of magnitude higher
than today.
The goal of this chapter is for architects to understand why vector is more general than mul-
timedia SIMD, as well as the similarities and differences between vector and GPU architec-
tures. Since vector architectures are supersets of the multimedia SIMD instructions, including
a beter model for compilation, and since GPUs share several similarities with vector architec-
tures, we start with vector architectures to set the foundation for the following two sections.
The next section introduces vector architectures, while Appendix G goes much deeper into the
subject.
4.2 Vector Architecture
The most efficient way to execute a vectorizable application is a vector processor.