Instruction-Level Parallelism and Its Exploitation - Computer Architecture: A Quantitative Approach - page 255

a. [25] <3.2> Assume a single-issue pipeline. Show how the loop would look both un-
scheduled by the compiler and after compiler scheduling for both floating-point oper-
ation and branch delays, including any stalls or idle clock cycles. What is the execution
time (in cycles) per element of the result vector, Y, unscheduled and scheduled? How
much faster must the clock be for processor hardware alone to match the performance
improvement achieved by the scheduling compiler? (Neglect any possible effects of
increased clock speed on memory system performance.)
b. [25] <3.2> Assume a single-issue pipeline. Unroll the loop as many times as necessary
to schedule it without any stalls, collapsing the loop overhead instructions. How many
times must the loop be unrolled? Show the instruction schedule. What is the execution
time per element of the result?
c. [25] <3.7> Assume a VLIW processor with instructions that contain five operations, as
shown in Figure 3.16 . We will compare two degrees of loop unrolling. First, unroll the
loop 6 times to extract ILP and schedule it without any stalls (i.e., completely empty
issue cycles), collapsing the loop overhead instructions, and then repeat the process
but unroll the loop 10 times. Ignore the branch delay slot. Show the two schedules.
What is the execution time per element of the result vector for each schedule? What
percent of the operation slots are used in each schedule? How much does the size of
the code differ between the two schedules? What is the total register demand for the
two schedules?
3.15 [20/20] <3.4, 3.5, 3.7, 3.8> In this exercise, we will look at how variations on Tomasulo's
algorithm perform when running the loop from Exercise 3.14 . The functional units (FUs)
are described in the table below.
Assume the following:
■ Functional units are not pipelined.
■ There is no forwarding between functional units; results are communicated by the
common data bus (CDB).
■ The execution stage (EX) does both the effective address calculation and the memory
access for loads and stores. Thus, the pipeline is IF/ID/IS/EX/WB.
■ Loads require one clock cycle.
■ The issue (IS) and write-back (WB) result stages each require one clock cycle.
■ There are five load buffer slots and five store buffer slots.
■ Assume that the Branch on Not Equal to Zero (BNEZ) instruction requires one clock
cycle.