Instruction-Level Parallelism and Its Exploitation - Computer Architecture: A Quantitative Approach - page 240

FIGURE 3.44 An overview of the four-core Intel i7 920, an example of a typical Arm A8
processor chip (with a 256 MB L2, 32K L1s, and no floating point), and the Intel ARM
230 clearly showing the difference in design philosophy between a processor intended
for the PMD (in the case of ARM) or netbook space (in the case of Atom) and a pro-
cessor for use in servers and high-end desktops . Remember, the i7 includes four cores,
each of which is several times higher in performance than the one-core A8 or Atom. All these
processors are implemented in a comparable 45 nm technology.
The Atom processors implement the x86 architecture using the standard technique of trans-
lating x86 instructions into RISC-like instructions (as every x86 implementation since the
mid-1990s has done). Atom uses a slightly more powerful microoperation, which allows an
arithmetic operation to be paired with a load or a store. This means that on average for a typ-
ical instruction mix only 4% of the instructions require more than one microoperation. The
microoperations are then executed in a 16-deep pipeline capable of issuing two instructions
per clock, in order, as in the ARM A8. There are dual-integer ALUs, separate pipelines for FP
add and other FP operations, and two memory operation pipelines, supporting more general
dual execution than the ARM A8 but still limited by the in-order issue capability. The Atom
230 has a 32 KB instruction cache and a 24 KB data cache, both backed by a shared 512 KB L2
on the same die. (The Atom 230 also supports multithreading with two threads, but we will
consider only one single threaded comparisons.) Figure 3.46 summarizes the i7, A8, and Atom
processors and their key characteristics.