Hardware Reference
In-Depth Information
FIGURE 3.31 Breakdown of the status on an average thread . “Executing” indicates the
thread issues an instruction in that cycle. “Ready but not chosen” means it could issue but an-
other thread has been chosen, and “not ready” indicates that the thread is awaiting the com-
pletion of an event (a pipeline delay or cache miss, for example).
Threads can be not ready due to cache misses, pipeline delays (arising from long latency in-
structions such as branches, loads, floating point, or integer multiply/divide), and a variety of
smaller effects. Figure 3.32 shows the relative frequency of these various causes. Cache effects
are responsible for the thread not being ready from 50% to 75% of the time, with L1 instruction
misses, L1 data misses, and L2 misses contributing roughly equally. Potential delays from the
pipeline (called “pipeline delay”) are most severe in SPECJBB and may arise from its higher
branch frequency.
 
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