Instruction-Level Parallelism and Its Exploitation - Computer Architecture: A Quantitative Approach - page 197

but unless speculative memory accesses are allowed, this improvement will
gain only 1 clock per iteration.
FIGURE 3.19 The time of issue, execution, and writing result for a dual-
issue version of our pipeline without speculation . Note that the LD following
the BNE cannot start execution earlier because it must wait until the branch out-
come is determined. This type of program, with data-dependent branches that
cannot be resolved earlier, shows the strength of speculation. Separate func-
tional units for address calculation, ALU operations, and branch-condition eval-
uation allow multiple instructions to execute in the same cycle. Figure 3.20
shows this example with speculation.