Instruction-Level Parallelism and Its Exploitation - Computer Architecture: A Quantitative Approach - page 188

The goal of the multiple-issue processors , discussed in the next few sections, is to allow mul-
tiple instructions to issue in a clock cycle. Multiple-issue processors come in three major la-
vors:
1. Statically scheduled superscalar processors
2. VLIW (very long instruction word) processors
3. Dynamically scheduled superscalar processors
The two types of superscalar processors issue varying numbers of instructions per clock and
use in-order execution if they are statically scheduled or out-of-order execution if they are dy-
namically scheduled.
VLIW processors, in contrast, issue a ixed number of instructions formated either as one
large instruction or as a fixed instruction packet with the parallelism among instructions expli-
citly indicated by the instruction. VLIW processors are inherently statically scheduled by the
compiler. When Intel and HP created the IA-64 architecture, described in Appendix H, they
also introduced the name EPIC—explicitly parallel instruction computer—for this architectur-
al style.
Although statically scheduled superscalars issue a varying rather than a fixed number of in-
structions per clock, they are actually closer in concept to VLIWs, since both approaches rely
on the compiler to schedule code for the processor. Because of the diminishing advantages of
a statically scheduled superscalar as the issue width grows, statically scheduled superscalars
are used primarily for narrow issue widths, normally just two instructions. Beyond that width,
most designers choose to implement either a VLIW or a dynamically scheduled superscalar.
Because of the similarities in hardware and required compiler technology, we focus on VLIWs
in this section. The insights of this section are easily extrapolated to a statically scheduled su-
perscalar.
Figure 3.15 summarizes the basic approaches to multiple issue and their distinguishing
characteristics and shows processors that use each approach.