Instruction-Level Parallelism and Its Exploitation - Computer Architecture: A Quantitative Approach - page 186

FIGURE 3.14 Steps in the algorithm and what is required for each step . For the issuing
instruction, rd is the destination, rs and rt are the sources, r is the reservation station alloc-
ated, b is the assigned ROB entry, and h is the head entry of the ROB. RS is the reservation
station data structure. The value returned by a reservation station is called the result . Register-
Stat is the register data structure, Regs represents the actual registers, and ROB is the reorder
buffer data structure.