Instruction-Level Parallelism and Its Exploitation - Computer Architecture: A Quantitative Approach - page 182

with ROB entry numbers in the Qj and Qk fields, as well as in the register status
fields, and we have added the Dest field to the reservation stations. The Dest
field designates the ROB entry that is the destination for the result produced by
this reservation station entry.
FIGURE 3.12 At the time the MUL.D is ready to commit, only the two L.D in-
structions have committed, although several others have completed exe-
cution . The MUL.D is at the head of the ROB, and the two L.D instructions are
there only to ease understanding. The SUB.D and ADD.D instructions will not com-
mit until the MUL.D instruction commits, although the results of the instructions
are available and can be used as sources for other instructions. The DIV.D is in
execution, but has not completed solely due to its longer latency than MUL.D .
The Value column indicates the value being held; the format #X is used to refer
to a value field of ROB entry X. Reorder buffers 1 and 2 are actually completed
but are shown for informational purposes. We do not show the entries for the
load/store queue, but these entries are kept in order.
The above example illustrates the key important difference between a processor with specu-
lation and a processor with dynamic scheduling. Compare the content of Figure 3.12 with that