Instruction-Level Parallelism and Its Exploitation - Computer Architecture: A Quantitative Approach - page 180

FIGURE 3.11 The basic structure of a FP unit using Tomasulo's algorithm and exten-
ded to handle speculation . Comparing this to Figure 3.6 on page 173, which implemented
Tomasulo's algorithm, the major change is the addition of the ROB and the elimination of the
store buffer, whose function is integrated into the ROB. This mechanism can be extended to
multiple issue by making the CDB wider to allow for multiple completions per clock.
Here are the four steps involved in instruction execution:
1. Issue —Get an instruction from the instruction queue. Issue the instruction if there is an
empty reservation station and an empty slot in the ROB; send the operands to the reser-
vation station if they are available in either the registers or the ROB. Update the control
entries to indicate the buffers are in use. The number of the ROB entry allocated for the
result is also sent to the reservation station, so that the number can be used to tag the res-
ult when it is placed on the CDB. If either all reservations are full or the ROB is full, then
instruction issue is stalled until both have available entries.
2. Execute —If one or more of the operands is not yet available, monitor the CDB while waiting
for the register to be computed. This step checks for RAW hazards. When both operands
are available at a reservation station, execute the operation. Instructions may take multiple