Hardware Reference
In-Depth Information
thus, the ROB supplies operands in the interval between completion of instruction execution
and instruction commit. The ROB is similar to the store buffer in Tomasulo's algorithm, and
we integrate the function of the store buffer into the ROB for simplicity.
Each entry in the ROB contains four fields: the instruction type, the destination field, the
value field, and the ready field. The instruction type field indicates whether the instruction is
a branch (and has no destination result), a store (which has a memory address destination), or
a register operation (ALU operation or load, which has register destinations). The destination
field supplies the register number (for loads and ALU operations) or the memory address (for
stores) where the instruction result should be writen. The value ield is used to hold the value
of the instruction result until the instruction commits. We will see an example of ROB entries
shortly. Finally, the ready field indicates that the instruction has completed execution, and the
value is ready.
Figure 3.11 shows the hardware structure of the processor including the ROB. The ROB sub-
sumes the store buffers. Stores still execute in two steps, but the second step is performed by
instruction commit. Although the renaming function of the reservation stations is replaced by
the ROB, we still need a place to buffer operations (and operands) between the time they issue
and the time they begin execution. This function is still provided by the reservation stations.
Since every instruction has a position in the ROB until it commits, we tag a result using the
ROB entry number rather than using the reservation station number. This tagging requires
that the ROB assigned for an instruction must be tracked in the reservation station. Later in
this section, we will explore an alternative implementation that uses extra registers for renam-
ing and a queue that replaces the ROB to decide when instructions can commit.
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