Hardware Reference
In-Depth Information
FIGURE 3.6 The basic structure of a MIPS floating-point unit using Tomasulo's al-
gorithm . Instructions are sent from the instruction unit into the instruction queue from which
they are issued in first-in, first-out (FIFO) order. The reservation stations include the operation
and the actual operands, as well as information used for detecting and resolving hazards.
Load buffers have three functions: (1) hold the components of the effective address until it is
computed, (2) track outstanding loads that are waiting on the memory, and (3) hold the results
of completed loads that are waiting for the CDB. Similarly, store buffers have three functions:
(1) hold the components of the effective address until it is computed, (2) hold the destination
memory addresses of outstanding stores that are waiting for the data value to store, and (3)
hold the address and value to store until the memory unit is available. All results from either
the FP units or the load unit are put on the CDB, which goes to the FP register file as well as
to the reservation stations and store buffers. The FP adders implement addition and subtrac-
tion, and the FP multipliers do multiplication and division.
The load buffers and store buffers hold data or addresses coming from and going to
memory and behave almost exactly like reservation stations, so we distinguish them only
when necessary. The floating-point registers are connected by a pair of buses to the functional
units and by a single bus to the store buffers. All results from the functional units and from
memory are sent on the common data bus, which goes everywhere except to the load buffer.
All reservation stations have tag fields, employed by the pipeline control.
Before we describe the details of the reservation stations and the algorithm, let's look at the
steps an instruction goes through. There are only three steps, although each one can now take
an arbitrary number of clock cycles:
 
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