Memory Hierarchy Design - Computer Architecture: A Quantitative Approach

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FIGURE 2.32 Early performance of various system calls under native execution, pure

virtualization, and paravirtualization .

2.22 [12] <2.4> Popek and Goldberg's definition of a virtual machine said that it would be in-

distinguishable from a real machine except for its performance. In this question, we will

use that definition to find out if we have access to native execution on a processor or are

running on a virtual machine. The Intel VT-x technology effectively provides a second set

of privilege levels for the use of the virtual machine. What would a virtual machine run-

ning on top of another virtual machine have to do, assuming VT-x technology?

2.23 [20/25] <2.4> With the adoption of virtualization support on the x86 architecture, virtual

machines are actively evolving and becoming mainstream. Compare and contrast the Intel

VT-x and AMD's AMD-V virtualization technologies. (Information on AMD-V can be

a. [20] <2.4> Which one could provide higher performance for memory-intensive applic-

ations with large memory footprints?

b. [25] <2.4> Information on AMD's IOMMU support for virtualized I/O can be found in

ation Technology and an input/output memory management unit (IOMMU) do to im-

prove virtualized I/O performance?

2.24 [30] <2.2, 2.3> Since instruction-level parallelism can also be effectively exploited on in-

order superscalar processors and very long instruction word (VLIW) processors with specula-

tion, one important reason for building an out-of-order (OOO) superscalar processor is the

ability to tolerate unpredictable memory latency caused by cache misses. Hence, you can

think about hardware supporting OOO issue as being part of the memory system! Look

at the floorplan of the Alpha 21264 in Figure 2.33 to find the relative area of the integer

and floating-point issue queues and mappers versus the caches. The queues schedule in-

structions for issue, and the mappers rename register specifiers. Hence, these are neces-

sary additions to support OOO issue. The 21264 only has L1 data and instruction caches on

chip, and they are both 64 KB two-way set associative. Use an OOO superscalar simulat-

for such as SimpleScalar ( www.cs.wisc.edu/~mscalar/simplescalar.html ) on memory-intensive

benchmarks to find out how much performance is lost if the area of the issue queues and

mappers is used for additional L1 data cache area in an in-order superscalar processor, in-

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