Memory Hierarchy Design - Computer Architecture: A Quantitative Approach - page 137

using the DDR2-667 and DDR2-533 DIMMs on a workload with 3.33 L2 misses per 1K in-
structions, and assume that 80% of all DRAM reads require an activate. What is the cost-
performance of the entire system when using the different DIMMs, assuming only one L2
miss is outstanding at a time and an in-order core with a CPI of 1.5 not including L2 cache
miss memory access time?
2.16 [12] <2.3> You are provisioning a server with eight-core 3 GHz CMP, which can execute
a workload with an overall CPI of 2.0 (assuming that L2 cache miss refills are not delayed).
The L2 cache line size is 32 bytes. Assuming the system uses DDR2-667 DIMMs, how many
independent memory channels should be provided so the system is not limited by memory
bandwidth if the bandwidth required is sometimes twice the average? The workloads in-
cur, on an average, 6.67 L2 misses per 1K instructions.
2.17 [12/12] <2.3> A large amount (more than a third) of DRAM power can be due to page ac-
tivation (see htp://download.micron.com/pdf/technotes/ddr2/TN4704.pdf and www.micron.com/
systemcalc ). Assume you are building a system with 2 GB of memory using either 8-bank
2 GB x8 DDR2 DRAMs or 8-bank 1 GB x8 DRAMs, both with the same speed grade. Both
use a page size of 1 KB, and the last level cacheline size is 64 bytes. Assume that DRAMs
that are not active are in precharged standby and dissipate negligible power. Assume that
the time to transition from standby to active is not significant.
a. [12] <2.3> Which type of DRAM would be expected to provide the higher system per-
formance? Explain why.
b. [12] <2.3> How does a 2 GB DIMM made of 1 GB x8 DDR2 DRAMs compare against a
DIMM with similar capacity made of 1 Gb x4 DDR2 DRAMs in terms of power?
2.18 [20/15/12] <2.3> To access data from a typical DRAM, we first have to activate the appro-
priate row. Assume that this brings an entire page of size 8 KB to the row buffer. Then we
select a particular column from the row buffer. If subsequent accesses to DRAM are to the
same page, then we can skip the activation step; otherwise, we have to close the current
page and precharge the bitlines for the next activation. Another popular DRAM policy is
to proactively close a page and precharge bitlines as soon as an access is over. Assume that
every read or write to DRAM is of size 64 bytes and DDR bus latency (Data out in Figure
2.30 ) for sending 512 bits is Tddr.
a. [20] <2.3> Assuming DDR2-667, if it takes five cycles to precharge, five cycles to activ-
ate, and four cycles to read a column, for what value of the row buffer hit rate ( r ) will
you choose one policy over another to get the best access time? Assume that every ac-
cess to DRAM is separated by enough time to finish a random new access.
b. [15] <2.3> If 10% of the total accesses to DRAM happen back to back or contiguously
without any time gap, how will your decision change?
c. [12] <2.3> Calculate the difference in average DRAM energy per access between the
two policies using the row buffer hit rate calculated above. Assume that precharging
requires 2 nJ and activation requires 4 nJ and that 100 pJ/bit are required to read or
write from the row buffer
2.19 [15] <2.3> Whenever a computer is idle, we can either put it in stand by (where DRAM
is still active) or we can let it hibernate. Assume that, to hibernate, we have to copy just the
contents of DRAM to a nonvolatile medium such as Flash. If reading or writing a cacheline
of size 64 bytes to Flash requires 2.56 μJ and DRAM requires 0.5 nJ, and if idle power con-
sumption for DRAM is 1.6 W (for 8 GB), how long should a system be idle to benefit from
hibernating? Assume a main memory of size 8 GB.