Memory Hierarchy Design - Computer Architecture: A Quantitative Approach - page 133

FIGURE 2.29 C program for evaluating memory system .
The program above assumes that program addresses track physical addresses, which is true
on the few machines that use virtually addressed caches, such as the Alpha 21264. In general,
virtual addresses tend to follow physical addresses shortly after rebooting, so you may need
to reboot the machine in order to get smooth lines in your results. To answer the questions
below, assume that the sizes of all components of the memory hierarchy are powers of 2. As-
sume that the size of the page is much larger than the size of a block in a second-level cache (if
there is one), and the size of a second-level cache block is greater than or equal to the size of a
block in a first-level cache. An example of the output of the program is plotted in Figure 2.30 ;
the key lists the size of the array that is exercised.
FIGURE 2.30 Sample results from program in Figure 2.29 .
2.4 [12/12/12/10/12] <2.6> Using the sample program results in Figure 2.30 :
a. [12] <2.6> What are the overall size and block size of the second-level cache?
b. [12] <2.6> What is the miss penalty of the second-level cache?
c. [12] <2.6> What is the associativity of the second-level cache?
d. [10] <2.6> What is the size of the main memory?
e. [12] <2.6> What is the paging time if the page size is 4 KB?
2.5 [12/15/15/20] <2.6> If necessary, modify the code in Figure 2.29 to measure the following
system characteristics. Plot the experimental results with elapsed time on the y -axis and
the memory stride on the x -axis. Use logarithmic scales for both axes, and draw a line for