Memory Hierarchy Design - Computer Architecture: A Quantitative Approach - page 128

atomic instructions to save and restore a VMCS. In addition to critical state, the VMCS in-
cludes configuration information to determine when to invoke the VMM and then speciically
what caused the VMM to be invoked. To reduce the number of times the VMM must be in-
voked, this mode adds shadow versions of some sensitive registers and adds masks that check
to see whether critical bits of a sensitive register will be changed before trapping. To reduce
the cost of virtualizing virtual memory, AMD's SVM adds an additional level of indirection,
called nested page tables . It makes shadow page tables unnecessary.
2.8 Concluding Remarks: Looking Ahead
Over the past thirty years there have been several predictions of the eminent [sic] cessation of the
rate of improvement in computer performance. Every such prediction was wrong. They were
wrong because they hinged on unstated assumptions that were overturned by subsequent events.
So, for example, the failure to foresee the move from discrete components to integrated circuits led
to a prediction that the speed of light would limit computer speeds to several orders of magnitude
slower than they are now. Our prediction of the memory wall is probably wrong too but it sug-
gests that we have to start thinking “out of the box.”
Wm. A. Wulf and Sally A. McKee
Hiting the Memory Wall: Implications of the Obvious
Department of Computer Science, University of Virginia (December 1994)
This paper introduced the term memory wall.
The possibility of using a memory hierarchy dates back to the earliest days of general-pur-
pose digital computers in the late 1940s and early 1950s. Virtual memory was introduced in
research computers in the early 1960s and into IBM mainframes in the 1970s. Caches appeared
around the same time. The basic concepts have been expanded and enhanced over time to
help close the access time gap between main memory and processors, but the basic concepts
remain.
One trend that could cause a significant change in the design of memory hierarchies is a
continued slowdown in both density and access time of DRAMs. In the last decade, both these
trends have been observed. While some increases in DRAM bandwidth have been achieved,
decreases in access time have come much more slowly, partly because to limit power con-
sumption voltage levels have been going down. One concept being explored to increase band-
width is to have multiple overlapped accesses per bank. This provides an alternative to in-
creasing the number of banks while allowing higher bandwidth. Manufacturing challenges to
the conventional DRAM design that uses a capacitor in each cell, typically placed in a deep
trench, have also led to slowdowns in the rate of increase in density. As this topic was going to
press, one manufacturer announced a new DRAM that does not require the capacitor, perhaps
providing the opportunity for continued enhancement of DRAM technology.
Independently of improvements in DRAM, Flash memory is likely to play a larger role be-
cause of potential advantages in power and density. Of course, in PMDs, Flash has already
replaced disk drives and offers advantages such as “instant on” that many desktop computers
do not provide. Flash's potential advantage over DRAMs—the absence of a per-bit transistor