Memory Hierarchy Design - Computer Architecture: A Quantitative Approach - page 122

FIGURE 2.24 The L2 and L3 data cache miss rates for 17 SPECCPU2006 benchmarks
are shown relative to all the references to L1, which also includes prefetches, speculat-
ive loads that do not complete, and program-generated loads and stores . These data,
like the rest in this section, were collected by Professor Lu Peng and Ph.D. student Ying
Zhang, both of Louisiana State University.