Memory Hierarchy Design - Computer Architecture: A Quantitative Approach - page 117

FIGURE 2.21 The Intel i7 memory hierarchy and the steps in both instruction and data
access . We show only reads for data. Writes are similar, in that they begin with a read (since
caches are write back). Misses are handled by simply placing the data in a write buffer, since
the L1 cache is not write allocated.
The instruction TLB is accessed to find a match between the address and a valid Page Table
Entry (PTE) (steps 3 and 4). In addition to translating the address, the TLB checks to see if the
PTE demands that this access result in an exception due to an access violation.