Hardware Reference
In-Depth Information
i7 uses 48-bit virtual addresses and 36-bit physical addresses, yielding a maximum physical
memory of 36 GB. Memory management is handled with a two-level TLB (see Appendix B,
Section B.4 ) , summarized in Figure 2.19 .
FIGURE 2.19 Characteristics of the i7's TLB structure, which has separate first-level in-
struction and data TLBs, both backed by a joint second-level TLB . The first-level TLBs
support the standard 4 KB page size, as well as having a limited number of entries of large 2
to 4 MB pages; only 4 KB pages are supported in the second-level TLB.
Figure 2.20 summarizes the i7's three-level cache hierarchy. The first-level caches are virtu-
ally indexed and physically tagged (see Appendix B, Section B.3 ), while the L2 and L3 caches
are physically indexed. Figure 2.21 is labeled with the steps of an access to the memory hier-
archy. First, the PC is sent to the instruction cache. The instruction cache index is
or 7 bits. The page frame of the instruction's address (36 = 48 − 12 bits) is sent to the instruc-
tion TLB (step 1). At the same time the 7-bit index (plus an additional 2 bits from the block of-
set to select the appropriate 16 bytes, the instruction fetch amount) from the virtual address is
sent to the instruction cache (step 2). Notice that for the four-way associative instruction cache,
13 bits are needed for the cache address: 7 bits to index the cache plus 6 bits of block off-set
for the 64-byte block, but the page size is 4 KB = 2 12 , which means that 1 bit of the cache index
must come from the virtual address. This use of 1 bit of virtual address means that the corres-
ponding block could actually be in two different places in the cache, since the corresponding
physical address could have either a 0 or 1 in this location. For instructions this does not pose
a problem, since even if an instruction appeared in the cache in two different locations, the
two versions must be the same. If such duplication, or aliasing, of data is allowed, the cache
must be checked when the page map is changed, which is an infrequent event. Note that a
very simple use of page coloring (see Appendix B, Section B.3 ) can eliminate the possibility of
these aliases. If even-address virtual pages are mapped to even-address physical pages (and
the same for odd pages), then these aliases can never occur because the low-order bit in the
virtual and physical page number will be identical.
 
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