Memory Hierarchy Design - Computer Architecture: A Quantitative Approach - page 111

memory requests. The first-level cache is virtually indexed and physically tagged, and the
second-level cache is physically indexed and tagged; both levels use a 64-byte block size. For
the D-cache of 32 KB and a page size of 4 KB, each physical page could map to two diferent
cache addresses; such aliases are avoided by hardware detection on a miss as in Section B.3 of
Appendix B.
Memory management is handled by a pair of TLBs (I and D), each of which are fully associ-
ative with 32 entries and a variable page size (4 KB, 16 KB, 64 KB, 1 MB, and 16 MB); replace-
ment in the TLB is done by a round robin algorithm. TLB misses are handled in hardware,
which walks a page table structure in memory. Figure 2.16 shows how the 32-bit virtual ad-
dress is used to index the TLB and the caches, assuming 32 KB primary caches and a 512 KB
secondary cache with 16 KB page size.
FIGURE 2.16 The virtual address, physical address, indexes, tags, and data blocks for
the ARM Cortex-A8 data caches and data TLB . Since the instruction and data hierarchies
are symmetric, we show only one. The TLB (instruction or data) is fully associative with 32
entries. The L1 cache is four-way set associative with 64-byte blocks and 32 KB capacity. The
L2 cache is eight-way set associative with 64-byte blocks and 1 MB capacity. This figure
doesn't show the valid bits and protection bits for the caches and TLB, nor the use of the way
prediction bits that would dictate the predicted bank of the L1 cache.