Hardware Reference
In-Depth Information
second rather than their clock rate, so a 133 MHz DDR chip is called a DDR266. Figure 2.14
shows the relationships among clock rate, transfers per second per chip, chip name, DIMM
bandwidth, and DIMM name.
DDR is now a sequence of standards. DDR2 lowers power by dropping the voltage from 2.5
volts to 1.8 volts and offers higher clock rates: 266 MHz, 333 MHz, and 400 MHz. DDR3 drops
voltage to 1.5 volts and has a maximum clock speed of 800 MHz. DDR4, scheduled for pro-
duction in 2014, drops the voltage to 1 to 1.2 volts and has a maximum expected clock rate of
1600 MHz. DDR5 will follow in about 2014 or 2015. (As we discuss in the next section, GDDR5
is a graphics RAM and is based on DDR3 DRAMs.)
Graphics Data RAMs
GDRAMs or GSDRAMs (Graphics or Graphics Synchronous DRAMs) are a special class of
DRAMs based on SDRAM designs but tailored for handling the higher bandwidth demands
of graphics processing units. GDDR5 is based on DDR3 with earlier GDDRs based on DDR2.
Since Graphics Processor Units (GPUs; see Chapter 4 ) require more bandwidth per DRAM
chip than CPUs, GDDRs have several important differences:1.
1. GDDRs have wider interfaces: 32-bits versus 4, 8, or 16 in current designs.
2. GDDRs have a higher maximum clock rate on the data pins. To allow a higher transfer rate
without incurring signaling problems, GDRAMS normally connect directly to the GPU and
are atached by soldering them to the board, unlike DRAMs, which are normally arranged
in an expandable array of DIMMs.
Altogether, these characteristics let GDDRs run at two to five times the bandwidth per DRAM
versus DDR3 DRAMs, a significant advantage in supporting GPUs. Because of the lower loc-
ality of memory requests in a GPU, burst mode generally is less useful for a GPU, but keeping
open multiple memory banks and managing their use improves effective bandwidth.
Reducing Power Consumption In SDRAMs
Power consumption in dynamic memory chips consists of both dynamic power used in a read
or write and static or standby power; both depend on the operating voltage. In the most ad-
vanced DDR3 SDRAMs the operating voltage has been dropped to 1.35 to 1.5 volts, signiic-
antly reducing power versus DDR2 SDRAMs. The addition of banks also reduced power, since
only the row in a single bank is read and precharged.
In addition to these changes, all recent SDRAMs support a power down mode, which is
entered by telling the DRAM to ignore the clock. Power down mode disables the SDRAM, ex-
cept for internal automatic refresh (without which entering power down mode for longer than
the refresh time will cause the contents of memory to be lost). Figure 2.15 shows the power
consumption for three situations in a 2 Gb DDR3 SDRAM. The exact delay required to return
from low power mode depends on the SDRAM, but a typical timing from autorefresh low
power mode is 200 clock cycles; additional time may be required for reseting the mode re-
gister before the first command.
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