Memory Hierarchy Design - Computer Architecture: A Quantitative Approach - page 99

FIGURE 2.14 Clock rates, bandwidth, and names of DDR DRAMS and DIMMs in 2010 .
Note the numerical relationship between the columns. The third column is twice the second,
and the fourth uses the number from the third column in the name of the DRAM chip. The fifth
column is eight times the third column, and a rounded version of this number is used in the
name of the DIMM. Although not shown in this figure, DDRs also specify latency in clock
cycles as four numbers, which are specified by the DDR standard. For example, DDR3-2000
CL 9 has latencies of 9-9-9-28. What does this mean? With a 1 ns clock (clock cycle is one-
half the transfer rate), this indicates 9 ns for row to columns address (RAS time), 9 ns for
column access to data (CAS time), and a minimum read time of 28 ns. Closing the row takes
9 ns for precharge but happens only when the reads from that row are finished. In burst mode,
transfers occur on every clock on both edges, when the first RAS and CAS times have
elapsed. Furthermore, the precharge is not needed until the entire row is read. DDR4 will be
produced in 2012 and is expected to reach clock rates of 1600 MHz in 2014, when DDR5 is
expected to take over. The exercises explore these details further.
Third, to overcome the problem of geting a wide stream of bits from the memory without
having to make the memory system too large as memory system density increased, DRAMS
were made wider. Initially, they offered a four-bit transfer mode; in 2010, DDR2 and DDR3
DRAMS had up to 16-bit buses.
The fourth major DRAM innovation to increase bandwidth is to transfer data on both the
rising edge and falling edge of the DRAM clock signal, thereby doubling the peak data rate.
This optimization is called double data rate (DDR).
To provide some of the advantages of interleaving, as well to help with power management,
SDRAMs also introduced banks , breaking a single SDRAM into 2 to 8 blocks (in current DDR3
DRAMs) that can operate independently. (We have already seen banks used in internal caches,
and they were often used in large main memories.) Creating multiple banks inside a DRAM
efectively adds another segment to the address, which now consists of bank number, row ad-
dress, and column address. When an address is sent that designates a new bank, that bank
must be opened, incurring an additional delay. The management of banks and row buffers
is completely handled by modern memory control interfaces, so that when subsequent access
speciies the same row for an open bank, the access can happen quickly, sending only the
column address.
When DDR SDRAMs are packaged as DIMMs, they are confusingly labeled by the peak
DIMM bandwidth. Hence, the DIMM name PC2100 comes from 133 MHz × 2 × 8 bytes, or 2100
MB/sec. Sustaining the confusion, the chips themselves are labeled with the number of bits per