Memory Hierarchy Design - Computer Architecture: A Quantitative Approach - page 96

column access strobe (CAS), follows it. These names come from the internal chip organization,
since the memory is organized as a rectangular matrix addressed by rows and columns.
FIGURE 2.12 Internal organization of a DRAM . Modern DRAMs are organized in banks,
typically four for DDR3. Each bank consists of a series of rows. Sending a PRE (precharge)
command opens or closes a bank. A row address is sent with an Act (activate), which causes
the row to transfer to a buffer. When the row is in the buffer, it can be transferred by success-
ive column addresses at whatever the width of the DRAM is (typically 4, 8, or 16 bits in DDR3)
or by specifying a block transfer and the starting address. Each command, as well as block
transfers, are synchronized with a clock.
An additional requirement of DRAM derives from the property signiied by its irst leter,
D , for dynamic . To pack more bits per chip, DRAMs use only a single transistor to store a bit.
Reading that bit destroys the information, so it must be restored. This is one reason why the
DRAM cycle time was traditionally longer than the access time; more recently, DRAMs have
introduced multiple banks, which allow the rewrite portion of the cycle to be hidden. In ad-
dition, to prevent loss of information when a bit is not read or writen, the bit must be “re-
freshed” periodically. Fortunately, all the bits in a row can be refreshed simultaneously just
by reading that row. Hence, every DRAM in the memory system must access every row with-
in a certain time window, such as 8 ms. Memory controllers include hardware to refresh the
DRAMs periodically.
This requirement means that the memory system is occasionally unavailable because it is
sending a signal telling every chip to refresh. The time for a refresh is typically a full memory
access (RAS and CAS) for each row of the DRAM. Since the memory matrix in a DRAM is
conceptually square, the number of steps in a refresh is usually the square root of the DRAM
capacity. DRAM designers try to keep time spent refreshing to less than 5% of the total time.
So far we have presented main memory as if it operated like a Swiss train, consistently deliv-
ering the goods exactly according to schedule. Refresh belies that analogy, since some accesses
take much longer than others do. Thus, refresh is another reason for variability of memory
latency and hence cache miss penalty.
Amdahl suggested as a rule of thumb that memory capacity should grow linearly with pro-
cessor speed to keep a balanced system, so that a 1000 MIPS processor should have 1000 MB of
memory. Processor designers rely on DRAMs to supply that demand. In the past, they expec-
ted a fourfold improvement in capacity every three years, or 55% per year. Unfortunately, the
performance of DRAMs is growing at a much slower rate. Figure 2.13 shows a performance