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cache. Assume the miss penalty to L2 is 10 cycles, and the L2 misses and penal-
ties are the same.
Answer
For floating-point programs, the average memory stall times are
The cache access latency (including stalls) for two-way associativity is 0.49/0.52
or 94% of direct-mapped cache. The caption of
Figure 2.5
says hit under one
miss reduces the average data cache access latency for floating point programs
to 87.5% of a blocking cache. Hence, for floating-point programs, the direct
mapped data cache supporting one hit under one miss gives beter performance
than a two-way set-associative cache that blocks on a miss.
For integer programs, the calculation is
The data cache access latency of a two-way set associative cache is thus 0.32/
0.35 or 91% of direct-mapped cache, while the reduction in access latency when
allowing a hit under one miss is 9%, making the two choices about equal.
The real difficulty with performance evaluation of nonblocking caches is that a cache miss
does not necessarily stall the processor. In this case, it is difficult to judge the impact of any
single miss and hence to calculate the average memory access time. The effective miss penalty
is not the sum of the misses but the nonoverlapped time that the processor is stalled. The be-
neit of nonblocking caches is complex, as it depends upon the miss penalty when there are
multiple misses, the memory reference patern, and how many instructions the processor can
execute with a miss outstanding.
In general, out-of-order processors are capable of hiding much of the miss penalty of an L1
data cache miss that hits in the L2 cache but are not capable of hiding a significant fraction
of a lower level cache miss. Deciding how many outstanding misses to support depends on a
variety of factors:
■ The temporal and spatial locality in the miss stream, which determines whether a miss can
initiate a new access to a lower level cache or to memory
■ The bandwidth of the responding memory or cache
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