Memory Hierarchy Design - Computer Architecture: A Quantitative Approach - page 79

For the four-way cache, the access time is 1.4 times longer. The elapsed time of
the miss penalty is 15/1.4 = 10.1. Assume 10 for simplicity:
Clearly, the higher associativity looks like a bad trade-off; however, since cache
access in modern processors is often pipelined, the exact impact on the clock
cycle time is difficult to assess.
Energy consumption is also a consideration in choosing both the cache size and associativ-
ity, as Figure 2.4 shows. The energy cost of higher associativity ranges from more than a factor
of 2 to negligible in caches of 128 KB or 256 KB when going from direct mapped to two-way
set associative.
FIGURE 2.4 Energy consumption per read increases as cache size and associativity
are increased . As in the previous figure, CACTI is used for the modeling with the same tech-
nology parameters. The large penalty for eight-way set associative caches is due to the cost
of reading out eight tags and the corresponding data in parallel.