Memory Hierarchy Design - Computer Architecture: A Quantitative Approach - page 75

4. Multilevel caches to reduce miss penalty —A difficult decision is whether to make the cache hit
time fast, to keep pace with the high clock rate of processors, or to make the cache large
to reduce the gap between the processor accesses and main memory accesses. Adding an-
other level of cache between the original cache and memory simplifies the decision (see
Figure 2.3 ) . The first-level cache can be small enough to match a fast clock cycle time, yet
the second-level (or third-level) cache can be large enough to capture many accesses that
would go to main memory. The focus on misses in second-level caches leads to larger
blocks, bigger capacity, and higher associativity. Multilevel caches are more power ei-
cient than a single aggregate cache. If L1 and L2 refer, respectively, to first- and second-
level caches, we can redefine the average memory access time: