Image Processing Reference
In-Depth Information
23.0 us
23.2 us
23.4 us
23.5 us
23.0 37 5 us
+62. 5 ns
+20 0.0 ns
+337 .5 ns
+37 5.0 ns
+41 2.5 ns
Ext_Clk
PLL_Clk1
Ext_ADC2
Ext_ADC1
Ext_ADC0
00004|RF_Fast_Trig
0|lpm_ff:$00000|dffs
0|lpm_ff:$00002|dffs
0|lpm_ff:$00004|dffs
0|lpm_ff:$00006|dffs
0|lpm_ff:$00008|dffs
0|lpm_ff:$00010|dffs
0|lpm_ff:$00012|dffs
0|lpm_ff:$00014|dffs
0|lpm_ff:$00016|dffs
0|lpm_ff:$00018|dffs
0|lpm_ff:$00020|dffs
0|lpm_ff:$00022|dffs
0|lpm_ff:$00024|dffs
0|lpm_ff:$00026|dffs
0|lpm_ff:$00028|dffs
0|lpm_ff:$00030|dffs
:$00060|Ena_A_reg
S:$00060|Ena_DCT
0060|Ena_DCT_del
48|SUB_TRIG_DCT
50|SUB_TRIG_DCT
52|SUB_TRIG_DCT
54|SUB_TRIG_DCT
56|SUB_TRIG_DCT
58|SUB_TRIG_DCT
60|SUB_TRIG_DCT
62|SUB_TRIG_DCT
64|SUB_TRIG_DCT
66|SUB_TRIG_DCT
68|SUB_TRIG_DCT
0|lpm_ff:$00076|dffs
60|SUB_TRIG_Occ
:$00060|SUB_TRIG
:$00060IFinal_DCT
000
150
000
000
150
000
40
140 107 84
70
60
53
49
46
44
42
41
40
40
140 107
70
60
53
49
44
42
41
40
40
140 107
70
60
53
49
44
42
41
40
40
140 107
70
60
53
49
44
42
41
40
40
140 107
70
60
53
49
44
42
41
40
40
140 107
70
60
53
49
44
42
41
40
40
140 107
70
60
53
49
44
42
41
40
40
140 107
70
60
53
49
44
42
41
40
40
140 107
70
60
53
49
44
42
41
40
40
140 107
70
60
53
49
44
42
41
40
40
140 107
70
60
53
49
44
42
41
40
40
140 107
70
60
53
49
44
42
41
40
40
140 107
70
60
53
49
44
42
41
40
40
140 107
70
60
53
49
44
42
41
40
40
140 107
70
60
53
49
44
42
41
40
40
140 107
70
60
53
49
44
42
41
40
40
140 107
70
60
53
49
44
42
41
40
0
1
0
9
3
1
0
1
0
Fig. 10. Simulation of the 1-fold spectral trigger simultaneously with the 3-fold threshold
trigger. The length of the shift registers = 16. Data in the Ext_ADC0 channel corresponds to a
muon signal with a 1-time-bin rising edge, 11-time-bins attenuation tail and with a constant
pedestal = 40 ADC-counts. Together with the begin of the muon peak (at 23.075
s), two
neighboring channels Ext_ADC1,2 are driven artificially to 150 ADC-counts to generate the
standard threshold trigger based on the 3-fold coincidence. The internal PLL clock = 80 MHz.
The internal standard threshold trigger appears 5 clock cycles later (+62.5 ns). The nodes
lpm_ff:$00000|dffs - lpm_ff:$00030|dffs correspond to the shift register x 15 ,..., x 0 . The system
is tuned for the Shape_A recognition (two 1st time bins on the pedestal level). Ena_A_reg is
generated (+200 ns = 16 clock cycles) due to the amplitude of the signal (140 ADC-counts) is
above the veto threshold. It is delayed next 15 cycles to be synchronized with
SUB_TRIG_Occ. Sub-triggers are generated 27 clock cycles (+337.5 ns) after the rising edge.
A calculation of the Occupancy takes next two clock cycles. 29 clock cycles after the rising
edge due to a coincidence of the Occupancy and Ena_DCT_del (inversion of the veto) the
SUB_TRIG is generated. Finally it appears in the same position as 3-fold coincidence
threshold trigger 31 clock cycles later. Final_DCT trigger corresponds to the possible
coincidence with a neighboring DCT "engines". If the standard threshold trigger(based on
3-fold coincidence) appears next any triggers are ignored though 768 clock cycles.
μ
The 16-point DCT with 16-stage shift register for 100 MHz sampling can cover 150 ns time
window. For the horizontal or very inclined showers this interval is sufficient for the analysis.
However, for the higher sampling frequency, when the time window may turn out too short,
the shift register may be extended from 16 to 24 stages and the eight samples for the higher
 
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