Image Processing Reference
In-Depth Information
allows implementation of fast multipliers from the DSP blocks and calculation of products in
a single clock cycle.
L
H
k
θ
k and
θ
are lower and upper scaled thresholds respectively, which are
set as external parameters.
According to (44) the calculation of a sub-trigger needs two multipliers, two comparators and
an AND gate. The multiplier stage of an embedded multiplier block supports 9
18
bit multipliers. Depending on the data width or operational mode of the multiplier, a single
embedded multiplier can perform one or two multiplications in parallel. Due to wide data
busses embedded multiplier blocks do not use the 9
×
9or18
×
9 mode in any multiplication. Each
multiplier utilizes two embedded multiplier 9-bit elements. The full DCT procedure needs
the calculation of all coefficients 70 DSP blocks. However, the scaling of X k in the last pipeline
chain is no longer needed. It is moved to the thresholds according to (44). Removing last
pipeline chain reduces amount of DSP blocks to 40. Sub-triggers routines (Fig. 9) need 2
DSP blocks each. The chip EP3C40F324I7 selected for the 4th generation of the 1st level SD
trigger contains 252 DSP 9-bit multipliers. So, for 3-fold coincidences and an implementation
of 3 "engines" the single DCT "engine" can support only 11 independent DCT coefficients
(Szadkowski, 2011). Sub-triggers A 0,1,2,3
k
×
k , C 0, k and D k are generated for the patterns A k ,
B k , C k and D k (k = 2,4,6) from Fig. 3, respectively. Sub-triggers are synchronized to each other
in shift registers in order to put simultaneously on an AND gate (Fig. 11). In order to keep
a trigger rate below the boundary deriving from the limited radio bandwidth, additionally
the amplitude of the jump is verified. If the jump is too weak, a veto comparator disables the
AND gate. Thus, if spectral coefficients
, B 0,1,2
ξ k match pattern ranges for each time bins selected by
multiplexer totally in 4 consecutive time bins and if veto circuit is enabled the final trigger is
generated. A delay time for the veto signal depends on the type of shape, which is an interest
of an investigation. For the single time bin of the rising edge the veto is delayed on 3 clock
cycles, for the investigated pattern corresponding to the three time bins of the rising edge the
maximal ADC value appears 2 clock cycles later in comparison to the previous case, so the
veto should be delayed on a single clock cycle only.
H 15 Ĭ H 13
H 15 Ĭ L 13
H 15 =ZS 1 X 1
X 1 = Ș 1 H 15
H 15
&
sub-trigger
H 13 =ZS 7 X 7
X 7 = Ș 7 H 13
H 13
H 13
Ȉ
H 15 Ĭ H 12
H 12 =ZS 9 X 9
X 9 = Ș 9 H 12
&
Occupancy
H 15 Ĭ L 12
…………………........
H 12
H 12
Next coefficient
Fig. 9. The structure of sub-triggers. The DCT coefficients X k are not directly calculated.
They have been replaced by a boundary of the acceptance lane: upper and lower thresholds
H 15 × θ
k , respectively. Signals between that thresholds (two comparators +
AND gate) generate preliminary sub-triggers, which are next summed and compared with
the arbitrary Occupancy level. If an amount of "fired" preliminary sub-triggers is above the
selected Occupancy, the final sub-trigger is generated for the next processes. It is
enabled/disabled depending on the veto variable, verifying the minimal amplitude of the
input signals to keep the trigger rate on the reasonable level and to prevent the saturation of
the transmission channel.
k
and H 15 × θ
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