Image Processing Reference
In-Depth Information
D 0,1
=
C 0
±
C 1
D 2
=
C 2
+
C 3
(36)
However, the 5th pipeline stage requires only a single multiplier for the E 2 variable:
D 6
D 4
D 6 +
D 4
E 2 =
S 4 D 2
E 0,1,3 =
D 0,1,3
E 4 =
E 6 =
(37)
D 12 +
D 8 E 8
D 12
D 8
=
±
=
±
=
=
E 7,11,15
5,9,13
D 7,11,15
D 5,9,13 E 14,10
D 14
D 10 E 12
(38)
The 6th stage does not require any multiplier, only 10 adders/sub-tractors and 6 shift registers
for synchronization:
=
E 3,5,7,9,13 ±
F 0,1.9.11.13.15 =
F 3,5,7,9,13
2.4.6.8.12
E 2,4,6,8,12
E 0,1.9.11.13.15
(39)
In the 7th pipeline stage 12 signals are delayed only for synchronization and 4 are scaled for
the following (n,k) pairs: (14,1),(12,7),(10,3),(8,5):
F n
2 S k
G n =
(40)
In the 8th pipeline stage pure registers for synchronization only are implemented for even
indices of X 0,2,4,6,8,10,12,14 and
H 9,11,13,15
8,10,12,14
=
G 9,11,13,15 ±
G 8,10,12,14
(41)
The last stage contains all scaling multipliers:
H m
4 2 cos k 32
X k
=
(42)
for the following (k,m) pairs: (1,15), (15,14), (7,13), (9,12), (3,11), (13,10), (5,9), (11,8), (14,7),
(2,6), (6,5), (10,4), (4,3), (12,2).
7. Implementation of the code into a FPGA
The spectral trigger should be generated if DCT coefficients normalized to the 1st harmonics
are in an arbitrary narrow range:
X k
X 1 = η k
H f ( k )
η 1
Thr k ξ k =
Thr k
H 15
(43)
where Thr k and Thr k are lower and upper thresholds for each spectral index k, respectively.
Altera ® Library of ParameterizedModules (LPM) contains the lpm_divide routine supporting
a division of fixed-point variables. However, this routine needs huge amount of logic elements
and it is slow (calculation requires 14 clock cycles in order to keep sufficiently high registered
performance). DSP blocks also do not support this routine. A simple conversion to
H 15 η 1
η k Thr k
H 15 η 1
η k Thr k
L
k
H
k
H 15 × θ
=
H f ( k )
=
H 15 × θ
(44)
 
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