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has been done to design efficient reverse converters. This chapter presents a study on the
state-of-the-art reverse converters which have been designed for the recently introduced
large dynamic range RNS four-moduli sets. We provide an overview about different reverse
conversion algorithms, the recent four-moduli sets, and the reverse converter architectures.
9. References
Bhardwaj, M., Premkumar, A. B. & Srikanthan, T. (1998). Breaking the 2 n -Bit Carry
Propagation Barrier in Residue to Binary Conversion for the [2 n -1, 2 n , 2 n +1] Modula
Set. IEEE Transactions on Circuits and Systems-I , Vol. 45, No. 9, pp. 998-1002.
Bhardwaj, M., Srikanthan, T. & Clarke, C.T. (1999). A reverse converter for the 4-moduli
superset {2 n -1, 2 n , 2 n +1, 2 n+1 +1}, Proceedings of IEEE Symposium on Computer
Arithmetic .
Cao, B., Chang, C.H. & Srikanthan, T. (2003). An Efficient Reverse Converter for the 4-
Moduli Set {2 n -1, 2 n , 2 n +1, 2 2 n +1} Based on the New Chinese Remainder Theorem.
IEEE Transactions on Circuits and Systems-I , Vol. 50, No. 10, pp. 1296-1303.
Cardarilli, G.C., Nannarelli, A. and Re, M. (2007). Residue Number System for Low-Power
DSP Applications, Proceedings of Asilomar Conference on Signals, Systems, and
Computers , Asilomar, USA.
Chaves, R. & Sousa, L. (2003). RDSP: A RISC DSP based on residue number system, Proceedings of
Euromicro Symposium on digital system design: architectures, methods and tools .
Conway, R. and Nelson, J. (2004). Improved RNS FIR Filter Architectures. IEEE Transactions
on Circuits and Systems-II , Vol. 51, No. 1, pp. 26-28.
Diclaudio, E., Piazza F. & Orlandi, G. (1995). Fast combinatorial RNS processors for DSP
applications. IEEE Transactions on Computers , Vol. 44, pp. 624-331.
Gallaher, D., Petry, F.E. & Srinivasan, P. (1997). The Digit Parallel Method for Fast RNS to
Weighted Number System Conversion for Specific Moduli (2 k -1, 2 k , 2 k +1). IEEE
Transactions on Circuits and Systems-II , Vol. 44, No. 1, pp. 53-57.
Hariri, A., Navi, K. & Rastegar, R. (2008). A new high dynamic range moduli set with
efficient reverse converter. Elsevier Journal of Computers and Mathematics with
Applications , Vol. 55, No. 4, pp. 660-668.
Hiasat A. & Abdel-Aty-Zohdy, H. S. (1998). Residue-to-binary arithmetic converter for the
moduli set (2 k , 2 k -1, 2 k -1 -1). IEEE Transactions on Circuits and System-II , Vol. 45, No.
2, pp. 204-208.
Hiasat, A. & Sweidan, A. (2004). Residue-to-binary decoder for an enhanced moduli set. IEE
Proc.-Comput. Digit. Tech. , Vol. 151, No. 2, pp. 127-130.
Jenkins, W. K. & Leon, B. J. (1977). The use of residue number systems in the design of finite
impulse response digital filters. IEEE Transactions on Circuits and Systems , Vol. CAS-
24, pp. 191-201.
Koc, C.K. (1989). A fast algorithm for mixed-radix conversion in residue arithmetic,
Proceedings of IEEE International Conference on Computer Design: VLSI in Computers
and Processors .
Lin, S.H., Sheu, M.H. & Wang, C.H. (2008). Efficient VLSI Design of a Residue-to-Binary
Converter for the moduli set (2 n , 2 n +1 -1, 2 n -1). IEICE Transactions on Information and
Systems , Vol. E91-D, No. 7, pp.2058-2060.
Mohan, P.V.A. (2002). Residue Number Systems: Algorithms and Architectures , Kluwer
Academic.
Mohan, P. V. A. (2007). RNS-To-Binary Converter for a New Three-Moduli Set {2 n+1 -1, 2 n ,
2 n -1}. IEEE Transactions on Circuits and Systems-II , Vol. 54, No. 9, pp. 775-779.
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