Image Processing Reference
In-Depth Information
XZ
2(2
nn
21
1)
Tx
2(
n
PT
)
(53)
1
Where
21
n
PH
2
TT
TTH
HH
(54)
21
n
10 2
n
10
2
n
2
n
1
Tv vvv
(55)
5
6
7
8
21
2
n
vx
xx
0 0
x
(56)
5
3,
n
1
3,1
3,0
3,
n
n
1
n
vK
KKK
KK
(57)
6
n
1
1
0
n
1
1
0
n
n
vx
xx
1 1
H
(58)
7
1,
n
1
1,1
1,0
2
n
n
1
n
vH
HH
(59)
8
2
n
1
1
0
2
n
Therefore, two modulo adders needed to realize (46) and (50). Moreover, (55) can be
implemented using three CSAs with EAC followed by a CPA with EAC. Note that some of
the full adders (FAs) of these CPAs and CSAs are simplified to XOR/AND or XNOR/OR
pairs due to the constant bits of the inputs. The final result, i.e. (53) can be obtained by a
(4
n
+1)-bit binaryadder with '1' carry-in. Fig. 3 presents the reverse converter for the moduli
set {2
n
-1, 2
n
, 2
n
+1, 2
2n
+1
-1}.
6. Reverse converter for the moduli set {2
n
-1, 2
n
+1, 2
2
n
, 2
2
n
+1
-1}
The moduli set {2
n
-1, 2
n
, 2
n
+1, 2
2n
+1
-1} reduces the total delay of RNS arithmetic unit versus the
moduli sets {2
n
-1, 2
n
, 2
n
+1, 2
2n
+1} and {2
n
-1, 2
n
+1, 2
2n
, 2
2n
+1}. However, still the inter-channel
delay of modulo 2
2n
+1
-1 is larger than the other three moduli, i.e. 2
n
-1, 2
n
and 2
n
+1. Due to this,
the moduli set {2
n
-1, 2
n
+1, 2
2
n
, 2
2
n
+1
-1} has been recently proposed by (Molahosseini & Navi,
2010). The main advantage of this set is that it provides all of the merits of the moduli set {2
n
-1,
2
n
, 2
n
+1, 2
2n
+1
-1} while providing larger dynamic range (6
n
-bit). Because, enhancing modulo 2
n
to 2
2
n
is not increasing the complexity of the reverse converter.
The converter of (Molahosseini & Navi, 2010) has a two-level architecutre. In other words,
they have used a combinatorial conversion algorithm; consisting both CRT and MRC. First,
the previous CRT-Based design of reverse converter for the subset {2
2
n
, 2
n
-1, 2
n
+1} (Hiasat &
Sweidan, 2004) is used to achieve the weighted equivalent of the residues (
x
1
,
x
2
,
x
3
) as below
Zx
2
2
n
Y
(60)
1
Where
Yvvvv
(61)
1
2
3
4
21
2
n