Image Processing Reference
In-Depth Information
vx
xxx
xx
(37)
1
1,2
n
1
1,1
1,0
2,2
n
2,2
2,1
2
n
2
n
vx
xx
0 0
(38)
2
2 ,2
n
2 ,1
2 ,0
21
n
21
n
vxx
0 0
x xx
0 0
x xx
(39)
31
3,1
3,0
3,
n
3,1
3,0
3,
n
3,3
3,2
n
1
n
1
n
1
n
1
v
x
x
x
x
1 1
x
x
x
1 1
(40)
32
2 ,0
3,
n
3,1
3,0
3,
n
3,1
3,0
n
1
n
2
n
1
n
1
v xxx
xxx
xxx
xxx
xx
(41)
4
4,1
4,0
4,
n
1
4,1
4,0
4,
n
1
4,1
4,0
4,
n
1
4,1
4,0
4,
n
1
4,3
4,2
n
n
n
n
2
Therefore, only five operands should be added using three CSAs with EAC followed by a
CPA with EAC (Piestrak, 1994, 1995). Hence, in comparison with (Cao et al., 2003) which
needed four CSAs, the (Molahosseini et al., 2010) results in reduction of one 4
n
-bit CSA with
EAC; while providing larger dynamic range. The Fig. 2 shows the hardware implementation
of this converter.
x
x
x
x
2
3
4
Operand Preparation Unit
4
n
-bit CSA with EAC
4
n
-bit CSA with EAC
4
n
-bit CSA with EAC
4
n
-bit CPA with EAC
x
Z
X
Fig. 2. The converter for moduli set {2
n
-1, 2
n
+1, 2
2n
, 2
2n
+1} (Molahosseini et al., 2010)
5. The reverse converter for the moduli set {2
n
-1, 2
n
, 2
n
+1, 2
2
n
+1
-1}
The main disadvantage of the moduli sets {2
n
-1, 2
n
, 2
n
+1, 2
2n
+1} and {2
n
-1, 2
n
+1, 2
2n
, 2
2n
+1} is
the modulo 2
2n
+1. Because, performance of modulo arithmetic circuits for 2
2n
+1 is much