Image Processing Reference
In-Depth Information
Fig. 32. FDMUX front end of SBC-FDFMUX filter bank according to Abdulazim et al. (2007));
z ν :
e j Ω ( ν ) ,
Ω ( ν ) =
=
ν =
0, 1, 2, 3, f 3 =
f d =
2
π
f / f ν ,
f n /8
and highpass filter transfer functions of stage
ν
, related to the original sampling rate 2 f
,
ν
are generated by the two branch filter transfer functions H
0, 1, in combination
with the simple “butterfly” across the output ports of each DF: Summation produces the
lowpass, subtraction the complementary highpass filter transfer function Bellanger (1989);
Kammeyer & Kroschel (2002); Mitra (1998); Schüssler (2008); Vaidyanathan (1993).
Assuming, for instance, a high-end input sampling frequency of f n
λ (
z ν )
,
λ =
=
=
2.4GHz
[Kopmann et al. (2003); Maufroid et al. (2003)], the operational clock rate of the third stage
is f 3
f 0
f n /2 3
=
=
300MHz, which is deemed feasible using present-day CMOS technology.
Hence, front-end parallelisation has to reduce operational clock of all subsystems preceding
the third stage down to f d =
=
300MHz. This is achieved by 8-fold parallelisation
of input branching and blocking (delay z 0 ), 4-fold parallelisation of the first stage of the
FDMUX tree (comprising input decimation by two, the PP branch filters H
f 3
λ (
z 1 )
λ =
0, 1,
and butterfly), and of the input branching and blocking (delay z 1 ) of the second stage and,
finally, corresponding 2-fold parallelisation of the two parallel 2-channel FDMUX FB of the
second stage of the tree, as indicated in Fig. 32.
The result of parallelisation, as required above, is shown in Fig. 33, where all interfractional
interfaces have been removed by straightforward application of identity of Fig.
,
30.
Subsequently, parallelisation of elementary subsystems is explained in detail:
1. Down-Sampling by M
2: In compliance with Fig. 31(b), each 2-fold down-sampler is
replaced with P ν units in parallel for 2 P ν -fold down-sampling with even time offset 2 p ,where
p
=
.
The result of 4-fold parallelisation of the front end input down-sampler of the upper branch
( ν =
=
0, 1, 2, 3 applies to the first tree stage
(
P 1
=
4
)
,and p
=
0, 1 to the second stage
(
P 2
=
2
)
is readily visible in Fig. 33 preceding filter MIMO block H 0 (
: In fact, it
represents an 8-to-4 parallelisation, where all odd PP components are removed according to
Fig. 31(b) Groth (2003).
2. Cascade of unit blocking delay and 2-fold down-sampler : For proper explanation, we first focus
on the input section of the first tree stage, lower branch
1,
λ =
0
)
z d
)
( ν = λ =
1
)
in front of filter block
Search WWH ::




Custom Search