Image Processing Reference
In-Depth Information
Next, Table 2 shows a summary of hardware resources used by the MPPA architecture in
the VLSI chip.
Function
Complexity
For m = 32
AND
m x m
1024
Adder
( m + 1) x m
1056
Mux
M
32
Flip-Flop
[(4 m + 2) x m ] + m
4160
Demux
M
32
Table 2. Summary of hardware resource utilization for the proposed MPPA architecture
Having analyzed Table 2, Fig. 4 and 5, one can deduce that the VLSI-FPGA platform based
on MPPAs via the HW/SW co-design reveals a novel high-speed SP system for the real time
enhacement/reconstruction of highly-computationally demanded RS systems. On one hand,
the reconfigurable nature of FPGAs gives an increased flexibility to the design allowing an
extra degree of freedoom in the partitioning stage of the pursued HW/SW co-design
technique. On the other side, the use of VLSI co-processors introduces a low power, high-
speed option for the implementation of computationally complex SP operations. The high-
level integration of modern ASIC technologies is a key factor in the design of bit-level
MPPAs. Considering these factors, the VLSI/ASIC approach results in an attractive option
for the fabrication of high-speed co-processors that perform complex operations that are
constantly demanded by many applications, such as real-time RS, where the high-speed
low-power computations exceeds the FPGAs capabilities.
5. Conclusions
The principal result of the reported study is the addressed VLSI-FPGA platform using
MPPAs via the HW/SW co-design paradigm for the digital implementation of the
RSF/RASF DEDR RS algorithms.
First, we algorithmically adapted the RSF/RASF DEDR-related techniques over the range
and azimuth coordinates of the uncertain RS environment for their application to imaging
array radars and fractional imaging SAR. Such descriptive-regularized RSF/RASF
algorithms were computationally transformed for their HW-level implementation in an
efficient mode using parallel computing techniques in order to achieve the maximum
possible parallelism in the design.
Second, the RSF/RASF algorithms based on reconstructive digital SP operations were
conceptualized and employed with MPPAs in context of the real time RS requirements.
Next, the bit-level array of processors elements of the selected reconstructive SP operation
was efficiently optimized in a high-speed VLSI architecture using 0.6um CMOS technology
with low-power standard cells libraries. The achieved VLSI accelerator was aggregated with
a reconfigurable FPGA device via HW/SW co-design paradigm.
Finally, the authors consider that with the bit-level implementation of specialized arrays of
processors in VLSI-FPGA platforms represents an emerging research field for the real-time
RS data processing for newer Geospatial applications.
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