Image Processing Reference
In-Depth Information
(near) real time implementation with existing Digital Signal Processors (DSP) or Personal
Computers (PC).
To treat such class of real time implementation, the use of specialized arrays of processors in
VLSI architectures as coprocessors or stand alone chips in aggregation with Field
Programmable Gate Array (FPGA) devices via the hardware/software (HW/SW) co-design,
will become a real possibility for high-speed Signal Processing (SP) in order to achieve the
expected data processing performance (Plaza, A. & Chang, 2008), (Castillo Atoche et al.,
2010a, 2010b). Also, it is important to mention that cluster-based computing is the most
widely used platform on ground stations, however several factors, like space, cost and
power make them impractical for on-board processing. FPGA-based reconfigurable systems
in aggregation with custom VLSI architectures are emerging as newer solutions which offer
enormous computation potential in both cluster-based systems and embedded systems area.
In this work, we address two particular contributions related to the substantial reduction of
the computational load of the Descriptive-Regularized RS image reconstruction technique
based on its implementation with massively processor arrays via the aggregation of high-
speed low-power VLSI architectures with a FPGA platform.
First, at the algorithmic-level, we address the design of a family of Descriptive-
Regularization techniques over the range and azimuth coordinates in the uncertain RS
environment, and provide the relevant computational recipes for their application to
imaging array radars and fractional imaging SAR operating in different uncertain scenarios.
Such descriptive-regularized family algorithms are computationally adapted for their HW-
level implementation in an efficient mode using parallel computing techniques in order to
achieve the maximum possible parallelism.
Second, at the systematic-level, the family of Descriptive-Regularization techniques based
on reconstructive digital SP operations are conceptualized and employed with massively
parallel processor arrays (MPPAs) in context of the real time SP requirements. Next, the
array of processors of the selected reconstructive SP operations are efficiently optimized in
fixed-point bit-level architectures for their implementation in a high-speed low-power VLSI
architecture using 0.5um CMOS technology with low power standard cells libraries. The
achieved VLSI accelerator is aggregated with a FPGA platform via HW/SW co-design
paradigm.
Alternatives propositions related to parallel computing, systolic arrays and HW/SW co-
design techniques in order to achieve the near real time implementation of the regularized-
based procedures for the reconstruction of RS applications have been previously developed
in (Plaza, A. & Chang, 2008), (Castillo Atoche et al., 2010a, 2010b). However, it should be
noted that the design in hardware (HW) of a family of reconstructive signal processing
operations have never been implemented in a high-speed low-power VLSI architecture
based on massively parallel processor arrays in the past.
Finally, it is reported and discussed the implementation and performance issues related to
real time enhancement of large-scale real-world RS imagery indicative of the significantly
increased processing efficiency gained with the proposed implementation of high-speed
low-power VLSI architectures of the descriptive-regularized algorithms.
2. Remote sensing background
The general formalism of the RS imaging problem presented in this study is a brief
presentation of the problem considered in (Shkvarko, 2006, 2008), hence some crucial model
elements are repeated for convenience to the reader.
Search WWH ::




Custom Search