Image Processing Reference
In-Depth Information
BB-Part
AP-Part
AP-SYS
CPU
CPD
VMON7
VMON2
MPEG4
VMON3
VMON5
VMON4
BB-
CPU
APL-RT
CPU
VMON6
VMONC
VMON1
11.15 mm
Fig. 9. Implementation example. This chip has three CPUs and several hardware accelerator
such as a moving picture encoder (MPEG-4). The 20-power domains for partial power-shut
down are implemented in a single LSI. This chip has a distributed common power domains
(CPD) whose power-down opportunity is very rare. Seven VMONs and one VMOC are
implemented in this chip.
Each VMON was only 2.52
m, and they can be designed as a fundamental
standard cell. Figure 10 shows the dependence of each VMON frequency on voltage, which
were between 2.9 and 3.1 mV/MHz.
In Fig. 10, the frequency of the ring oscillators was designed to be about 200 MHz. Time
resolution was about 5 ns. Note that we used LeCroy's SDA 11000 XXL oscilloscope with
a 100-M-word-long time-interval recording memory and a maximum sampling speed of 40
GS/s.
μ
m
×
25.76
μ
3.1 Dhrystone measurement
We show the results of measurements taken while executing the Dhrystone benchmark
program in the APL-RT CPU and a system control program in the AP-SYS CPU. The
Dhrystone is known as a typical benchmark program for measuring performance per unit
power, MIPS/mW, and the activation ratio of the circuit in the CPU core is thus high. Figure 11
shows the local supply noise fromVMON1 embedded in the APL-RT CPU that was measured
while executing the Dhrystone benchmark program. In these measurements, the cache of the
APL-RT CPU was ON, and the hit ratio of the cache was 100%. This is the heaviest load for
the APL-RT CPU executing the Dhrystone program. The measured maximum local supply
noise was 69 mV under operation of the APL-RT CPU at 312 MHz and V DD =1.25 V. In this
measurement, the baseband part was powered on, but the clock distribution was stopped.
 
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