MODELING AND BUDGETING OF TIMING JITTER AND NOISE - Advanced Signal Integrity for High-Speed Digital Design - page 584

1.2

1.1

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0.0

− 0.1

Zero ISI Zero ISI

− 0.2

− 0.3

0123456789 0 1 2 3 4 5
Time (ns)

Figure 13-24 Pulse response with ISI terms.

+

8000 waveforms. To begin to understand how we can use superposition, we

present another example.

Example 13-8 Using Superposition to Find the Worst-Case Bit Pattern Refer-
ring to Figure 13-24, we observe that if we were to transmit a second pulse at
t =

4 ns (the second postcursor position), superposition will cause the signal level
of the second pulse to be reduced by the amount of negative ISI at that position.
As a result, the value of the second pulse is 1 . 111 V

− =

0 . 864 V. This
tells us that the worst-case pattern for a logical 1 should include a 101 subpattern.
If we launch a third pulse starting at t =

0 . 247 V

8 ns (the sixth postcursor position),

it will be affected negatively by the − 0.247-V ISI from the second pulse and

by the 0.012-V ISI from the first pulse, degrading it to a value of 0.852 V.

Thus, we expand the worst-case bit pattern so that it now includes 1000101.
Launching a fourth pulse at the tenth postcursor position adds an additional
1 mV of degradation to a logical 1 signal. The pulse shows no negative ISI beyond
the tenth postcursor, so we don't need to carry the analysis any further. The
waveform for a worst-case pattern will contain 10001000101. We demonstrate
the analysis graphically in Figure 13-25a. The voltage will be

−

1 . 111 V − 0 . 247 V − 0 . 012 V − 0 . 001 V = 0 . 851 V

which corresponds to the value of a worst-case 1.
We find the pattern that results in the worst-case zero using the same approach.
However, in this case, we focus on the bit positions that exhibit positive ISI. The
fourth, eighth, and twelfth postcursors have positive ISI of 0.055, 0.003, and
0.0001 V, respectively. Figure 13-25b shows the analysis and the worst-case bit