MODELING AND BUDGETING OF TIMING JITTER AND NOISE - Advanced Signal Integrity for High-Speed Digital Design - page 576

2.5 V
12.5 W

+

50 W

50 W

V ref −

(a)

+ Z odd = 50 W

50 W

0 ↔ 10 mA
200 W

50 W

Z odd = 50 W

−

(b)

Figure 13-19 Circuits for Example 13-6: (a) single-ended system; (b) differential
system.

The differential signaling system shown in Figure 13-19b is designed to oper-
ate at 5 Gb/s over a lossy interconnect that requires equalization. It employs a
10-mA current-mode transmitter to provide a singled swing of 400 mV when
driving the parallel combination of transmitter impedance and transmission line.
The differential circuit also uses a 2.5 V supply with a 10% budget for supply
noise. However, the combination of high transmitter impedance and the differ-
ential receiver is expected to reject more than 99% of the supply noise. The
crosstalk budget is reduced to 5% of the signal swing due to reduced coupling of
the differential transmission lines and the common-mode rejection of the receiver.
The ISI budget remains at 10% of the signal swing. The equalizer uses a 4-bit
DAC and is designed to provide a maximum of 20% equalization. The receivers
for both designs are differential and have similar offsets and sensitivities which
we estimate at 35 and 10 mV, respectively. Finally, we include thermal and shot
noise in both interfaces, specifying that the probability of exceeding the budgeted
noise cannot exceed 10 − 12 .
Table 13-5 summarizes the contributions of the individual noise sources that
we discussed above. From the table we see that the projected worst-case noise is
835 mV for the single-ended system and 114 mV for the differential system. A
widely used metric for judging the noise characteristics of a digital system is the
noise margin, which we introduced in Chapter 12. We can use equations (12-3a)
and (12-3b) to develop a system noise margin:

v NM = v NMl + v NMh = (v oh, min − v ol, max ) − (v ih, max − v il, min )