MODELING AND BUDGETING OF TIMING JITTER AND NOISE - Advanced Signal Integrity for High-Speed Digital Design - page 566

TABLE 13-2. PCI Express 2.5-Gb/s Jitter Budget at 10 − 12 BER
Component

Term σ RJ (ps) DJ δδ (ps) TJ (ps)

Reference clock TJ clock 4.7 41.9 108

Transmitter TJ TX 2.8 60.6 100

Channel TJ channel 0 90 90

Receiver TJ Rx 2.8 120.6 147

Linear TJ 458

RSS TJ 86.5 313.1 399.6

4

1

Initial Jitter Targets Finish Design

7

2 5

Build &
Measure
Hardware

Design Option Exploration
(Tx, Rx, CLK, Channel)

Final
Simulations

Yes

Yes

Working
Budget?

Working
Budget?

Working
Budget?

No No No

Yes

3

Trade-off/Adjust Targets
or Modify Design

Trade-off/Adjust Targets

Done

6

Figure 13-16 System design flow.

understanding of the design behavior provided by statistical analysis methods is
especially helpful in minimizing the number of iterations.
Step 4: The component and board designs are completed after closing the
budget. This includes layout, design rule check, and extraction of final models
from the board, package, and I/O circuit designs.
Step 5: A final set of simulations with the extracted models for verification
purposes is recommended prior to building hardware. This step provides the
design team with a final chance to identify and correct design issues. Finding
issues in simulation is faster and less expensive than waiting until hardware is
in the lab.
Step 6: As was the case with the exploratory analysis, it may be necessary
to adjust the timing targets or to modify some parts of the system design at this
stage, although the use of statistical analysis methods reduces the likelihood that
changes will be required at this stage.
Step 7: Finally, we reach the last major step in the process: hardware building
and measurement. The design process is structured to minimize the risk of finding
issues at this stage, but the ultimate measure of success is functioning systems.