MODELING AND BUDGETING OF TIMING JITTER AND NOISE - Advanced Signal Integrity for High-Speed Digital Design - page 564

systems include data transmitters and receivers, interconnect channels, and clock
sources. In designing a system, we must account for the DJ and RJ from each.
Example 13-2 2.5-Gb/s PCI Express System Jitter Budget To illustrate, we
use the system jitter budget for the first-generation PCI Express (PCIe) interface.
Figure 13-15a depicts the main components of a PCIe link. PCI Express systems
do not distribute a global high-frequency I/O clock, but instead, use I/O clocks
that are locally generated from a low-frequency reference clock, often using
phase-locked loops (PLLs). In addition, a clock-and-data recovery (CDR) circuit
at the receiver handles synchronization of the data signals [Martwick, 2005].
Figure 13-15b contains a block diagram that describes the system model for
the generation and propagation of jitter in a PCI Express link. The 100-MHz
reference clock generates jitter, TJ refclk , which enters the phase-locked loops for
both the transmitter and receiver. The PLLs act as high-pass filters that allow
high-frequency jitter to pass through them. In addition, each will also act as
a source of additional jitter (TJ Tx , gen and TJ Rx , gen ) caused by noise introduced
both locally (e.g., thermal noise) and by the system (e.g., supply noise). The
channel adds jitter (TJ chan ) due to ISI and crosstalk, but is assumed not to filter
the incoming jitter noticeably. The comparator function reflects the fact that both
PLLs track the jitter, so that the jitter propagation due to the transmitter and
receiver is a function of the difference in their transfer functions. Intuitively, if
both PLLs have the same impulse response, they will pass identical jitter, given
the same input, TJ refclk . As a result, the receiver will tend to track the jitter passed
by the transmitter, and the total jitter from the reference clock that gets passed
by the PLLs is determined by the difference in their transfer functions. Finally,
the CDR circuit will also filter the jitter.
Having identified the main sources of jitter, we can write expressions for the
system DJ and RJ:

DJ δδ ( sys ) = DJ δδ ( Tx ) + DJ δδ ( channel ) + DJ δδ ( Rx ) + DJ δδ ( clock ) (13-19)

σ RMS ( Tx )

σ RMS ( channel ) σ RMS ( Rx ) σ RMS ( clock )

(13-20)

σ RMS ( sys ) = + + +

Equations (13-10), (13-13), and (13-14) provide the fundamental jitter relations
that we use to budget the jitter for a PCI Express system, which is shown in
Table 13-2. What they do not do, however, is to tell us how to use them to develop
a jitter budget that results in a successful system design. Doing so successfully
requires that we use the equations within the context of a design methodology.
We offer an example of a contemporary design methodology in Figure 13-16 and
we describe the individual steps below.
Step 1: Negotiate initial targets. The targets are most often based on engineer-
ing judgment and experience with prior designs. In addition to providing the I/O
and signal integrity engineers with targets for their designs, they also provide the
team with the means for making trade-offs in order to keep the budget balanced
as the design proceeds.