MODELING AND BUDGETING OF TIMING JITTER AND NOISE - Advanced Signal Integrity for High-Speed Digital Design - page 559

0.1

0.08

0.06

0.04

0.02

0

− 40 − 20 0 20 40

Jitter (ps)

(e)

0.02

0.016

0.012

0.008

0.004

0

− 40 − 20

0 20 40

Jitter (ps)

(f)

0.015

0.012

0.009

0.006

0.003

0

− 40 − 20

0 20 40

Jitter (ps)

(g)

Figure 13-11 ( Continued )

where A is the amplitude of the periodic jitter and t is the time relative to the

ideal edge position.

Duty Cycle Distortion (DCD) Duty cycle distortion results from variation in the
amount of time that the signal spends in the logic states, such as rise and fall
time mismatch. The probability density function for jitter caused by duty cycle
distortion is the sum of two delta functions:

2 δ t −

+ δ t +

1 α DCD

2

α DCD
2

PDF DCD (t) = (13-12)

In equation (13-12), α DCD is the peak-to-peak duty cycle distortion and t is
the time relative to the ideal edge position. The PDF for duty cycle distortion
jitter is shown in Figure 13-11b.