Digital Signal Processing Reference
In-Depth Information
Linear Equalizer
Enhanced
Noise
Equalized Channel
Channel
Noise
f [GHz]
Figure 12-34 Noise enhancement in a linear equalizer.
12.3.4 Nonidealities in DLEs
Thus far we have assumed that the equalizers operate with ideal characteristics
in our analysis. Of course, since real implementations will not behave in an
ideal fashion, we offer a brief discussion of the limitations of discrete linear
equalizers. We begin by pointing out that a practical equalizer implementation
has limited resolution on the tap coefficients. Our previous analysis has assumed
that we can set the tap coefficients with resolution down 0.001. Tap coefficient
values are often set using current digital-to-analog converters (DACs) that bias
the transmitter tail currents [Dally and Poulton, 1997]. Achieving a tap resolution
of 0.001 would entail using a 10-bit binary weighted DAC, which is likely to
consume excessive silicon area and power. As a point of comparison, Jaussi
et al. [2005] used a 6-bit DAC for a four-tap equalizer that achieved 8 Gb/s
over a 102-cm PCB-based channel. Other nonidealities include errors in the
sampled voltage due to sampling jitter and charge leakage, quantization noise of
the analog-to-digital conversion, nonlinearity of the equalizer taps and summing
circuits, and offset currents due by device mismatch. [Jaussi et al., 2005].
Finally, discrete linear equalizers do not distinguish between signal and noise,
so they filter both the signal and noise, as shown in Figure 12-34. As a result,
DLEs do not improve signal/noise ratio. Instead, the performance gain is due
to the increase in usable bandwidth provided by the flattening of the frequency
response, as discussed earlier.
12.3.5 Adaptive Equalization
At intermediate data rates, the equalizer coefficients are often set based on the
average characteristics of the interconnect channel. For example, the PCI Express
interface calls for
3 . 5 dB of equalization for PCB-based interconnects of up
 
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