Digital Signal Processing Reference
In-Depth Information
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Figure 12-11
Example interconnect channel impact on a 10-Gb/s signal waveform:
(a) transmitter output; (b) receiver input.
Figures 12-13 and 12-14 demonstrate, an idealized equalizer would completely
reverse the effects of the interconnect, restoring the signal to its original form,
exactly matching the waveform and eye at the transmitter output.
In practice, power and device count limitations make the design of a perfect
equalizer impractical. However, we do not require ideal implementation in order
to realize the benefits of equalization, as we shall see in the remaining sections
of this chapter. In subsequent sections we explore the design, operation, and
limitations of the different types of equalizers that find use in multi-Gb/s sig-
naling systems now and in the future. Equalization is an area in which there is
considerable ongoing research and one that has many possible implementations.
Although we present some representative examples, the nuances of equalizer
design implementations are beyond our scope. Instead, we focus on developing a
solid understanding of their behavior in terms of fundamental building blocks so
that we may use them effectively to maximize the performance of our signaling
systems.
12.2 CONTINUOUS-TIME LINEAR EQUALIZERS
Continuous-time linear equalizers (CTLEs) are analog in nature, operating con-
tinuously as the name implies. This is in contrast to discrete-time equalizers,
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