EQUALIZATION - Advanced Signal Integrity for High-Speed Digital Design - page 494

12

EQUALIZATION

12.1 Analysis and design background 500

12.1.1 Maximum data transfer capacity 500

12.1.2 Linear time-invariant systems 502

12.1.3 Ideal versus practical interconnects 506

12.1.4 Equalization overview 511

12.2 Continuous-time linear equalizers 513

12.2.1 Passive CTLEs 514

12.2.2 Active CTLEs 521

12.3 Discrete linear equalizers 522

12.3.1 Transmitter equalization 525

12.3.2 Coefficient selection 530

12.3.3 Receiver equalization 535

12.3.4 Nonidealities in DLEs 536

12.3.5 Adaptive equalization 536

12.4 Decision feedback equalization 540

12.5 Summary 542

References 545

Problems 546

We have already discussed the impact of Moore's law, which drives the interchip
data bandwidth to continually increasing performance levels. We have also shown
that nonideal aspects of transmission lines, such as crosstalk and losses, can have
a significant impact on signal integrity and timing. These impacts dominate at
multi-Gb/s speeds, causing “smearing” of signals so that their energy is spread
over multiple bit positions, a phenomenon known as intersymbol interference
(ISI). The impact of ISI is an increase in the jitter that degrades the timing
margin and a distortion in the signal levels that degrades the voltage margin of
the interchip signaling link. Equalization is a circuit technique that reduces the