I/O CIRCUITS AND MODELS - Advanced Signal Integrity for High-Speed Digital Design - page 488

5.000ns 0.000 0.000 0.000

|
[Rising Waveform]

typ min max
R fixture

= 50

V fixture 3.3

V fixture min

=

= 3.15

V fixture max = 3.45

0.000ns 0.000 0.000 0.000

0.300ns 0.050 0.040 0.060

... ... ... ...

5.000ns 3.300 3.150 3.450

|
|******************************************************
[End]

11.11 SUMMARY

In this chapter we described the operation and modeling of contemporary
high-speed I/O circuits, including transmitters, receivers, and on-die terminations.
Insight into the behavior of these circuits is critical to designing successful
high-speed signaling solutions. The signal integrity engineer who gains sufficient
understanding to interact successfully with his or her I/O circuit counterpart will
have a key tool for optimizing a signaling system design for high-speed operation.

REFERENCES

I/O circuit design remains an area of active research, with dozens of papers published
in conference proceedings and technical journals each year. We do not attempt here to
provide an exhaustive survey of the published literature. For more complete treatments
of I/O and ESD circuits, we refer the reader to Dabral and Maloney [1997] and Dally
and Poulton [1997]. The work by Dabral and Maloney focuses more on basic techniques,
whereas Dally and Poulton offer a more comprehensive approach. Granberg [2004] com-
piled a comprehensive reference that includes technical data on a wide variety of I/O
techniques and standards, including memory and multi-Gb/s serial links.

Boni, Andrea, Andrea Pierazzi, and Davide Vecchi, 2001, LVDS I/O interface for
Gb/s-per-pin operation in 0.35-

m CMOS, IEEE Journal of Solid-State Circuits , vol. µ

36, no. 4, Apr., pp. 706-711.
Chappell, Barbara, et al., 1998, Fast CMOS ECL receivers with 100-mV worst-case
Sensitivity, IEEE Journal of Solid-State Circuits , vol. 23, No. 1, Feb., pp. 59-67.
Dabral, Sanjay, and Timothy Maloney, 1998, Basic ESD and I/O Design ,

Wiley-Interscience, New York.