Digital Signal Processing Reference
In-Depth Information
V
TT
= 1.0 V
R
TT
= 50
Ω
t
= 1 ns
i
75
W
, 0.5
ns
50
W
, 1
ns
z
=
l
2
z
= 0
z
=
l
1
Board 1
Board 2
R
s
= 12.5
Ω
(a)
l
2
z
Γ
T2
1
−
0.2 0.2
0
0.8
1.2
1
v
(
z
= 0)
i
(
z
= 0)
v
(
z
=
l
)
i
(
z
=
l
)
0.200 V
16.00 mA
1 ns
0.200 V
16.00 mA
1.400 V
0.00 mA
2 ns
2.5 ns
0.920 V
0.00 mA
3 ns
1.160 V
3.20 mA
3.5 ns
1.016 V
0.00 mA
4 ns
−
0.64 mA
0.968 V
4.5 ns
0.996 V
0.00 mA
5 ns
1.006 V
0.13 mA
5.5 ns
1.000 V
0.00 mA
6 ns
0.999 V
−
0.03 mA
6.5 ns
1.000 V
0.00 mA
t
(b)
Transmitter
Receiver
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
0
1
2
3
4
5
6
7
Time (ns)
(c)
Figure 11-27
Open-drain interconnect and analysis for Example 11-5: (a) circuit;
(b) lattice diagram; (c) waveform.
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