Digital Signal Processing Reference
In-Depth Information
60
58
56
W
m
L
=
0.25
µ
m
=
65
µ
W
m
L
=
0.25
µ
m
=
80
µ
54
52
v
x
50
i
x
48
46
44
42
40
0
0.5
1
1.5
2
2.5
v
x
(V)
(a)
3.0
Transmitter
2.5
Receiver
2.0
1.5
1.0
12.5
Ω
50
Ω
, 1.7 ns
0.0 V
2.5 V
t
r
=
50 ps
→
0.5
0.0
0.0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
Time (ns)
(b)
Figure 11-17
Example on-chip termination using parallel FETs: (a) FET termination
circuit and resistance as a function of line voltage; (b) example waveform.
11.5.3 Advanced design considerations
The primary motivation for implementing on-chip termination is to minimize
reflections by eliminating the transmission line stub that is typically required
when terminating on the printed circuit board. To fully realize the potential
benefit of on-chip termination, automatic impedance control similar to the
impedance-matching technique described in Section 11.2.4 is commonly used.
In addition, designers may implement techniques to improve the linearity of the
on-chip termination [Dally and Poulton, 1997].
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